Chip scale 12-channel 10 Gb/s optical transmitter and receiver sub-assemblies based on wet etched silicon interposer
ArticleLi, C., Li, T., Guelbenzu de Villota, G., Smalbrugge, B., Stabile, P. & Raz, O. (2017). Chip scale 12-channel 10 Gb/s optical transmitter and receiver sub-assemblies based on wet etched silicon interposer. Journal of Lightwave Technology, 35(15), 3229-3236. In Scopus Cited 4 times.
In this paper, compact optical sub-assemblies are demonstrated based on a novel silicon interposer, which is designed and fabricated in a wafer scale process. The interposer includes the design of optical and electrical connections. A low cost fabrication method, wet etching, is used to define light inputs and outputs as well as create the required recesses in the interposer to embed the chips into the silicon wafer at the same time. Impedance matched traces, for the high speed signals of the CMOS and opto-electronic ICs, are designed using advanced design system (ADS) software and transferred onto the interposer by photolithography and electro-plating, which are accomplished on the deeply etched topology. The whole process flow of the silicon interposer patterning is designed and demonstrated, and the challenges are discussed. After the process, the optoelectronic dies and their complimentary CMOS parts are flipped and bonded on the interposer in close proximity, and a mechanical optical interface (MOI) is mounted for light coupling. Both transmitter and receiver sub-assemblies provide 12 parallel optical interconnections, and are scaled down to an area measuring 6 by 8 millimeters. Signal integrity testing is performed on a probe station for 10 Gb/s data signal delivering clear eye patterns for all channels (in both Rx and Tx sub-assemblies). The performance is further characterized using bit error rate (BER) testing. Both transmitter and receiver assemblies outperform a reference SFP+, with receiver sensitivity of -10 dBm at a BER lower than 10-12 after compensating for the MOI insertion loss. Finally, we also test the assemblies for crosstalk and demonstrate that the current design has a maximal additional penalty lower than 0.2 dB and 0.8 dB for transmitter and receiver respectively.