Learning hardware using multiple-valued logic - Part 1: Introduction and approach
ArticlePerkowski, M.A., Foote, D., Chen, Qihong, Al-Rabadi, A. & Jozwiak, L. (2002). Learning hardware using multiple-valued logic - Part 1: Introduction and approach. IEEE Micro : Chips, Systems, Software and Applications, 22(3), 41-51. In Scopus Cited 9 times.
The authors propose a learning-hardware approach as a generalization of evolvable hardware. A massively parallel, reconfigurable processor speeds up logic operators performed in learning hardware. The approach uses combinatorial synthesis methods developed within the framework of the logic synthesis in digital-circuit-design automation