Important for our research are data converters based on sigma-delta modulation (SDM). We are working on the improvement of smart SDMs by applying our new limit-cycle theory to optimally correct their loop filters, their feedback DA converters and for stability estimation. We found new incremental methods, including a new decoding technique for highly accurate DC sensing with SDMs. In parallel we do research on ultra-high-speed SDM AD converters, using novel architectures that significantly relax the design requirements for meta-stability errors, for excess loop delay and for DAC jitter.
We derive and implement very high-speed high-resolution AD converter architectures, using a novel parallel sampling technique, exploiting information about the input signal distribution function.
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Our most recent peer reviewed publications
A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 (2018)
A 2 GHz 0.98 mW 4-bit SAR-based quantizer with ELD compensation in an UWB CT ΣΔ modulator2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 (2018)
Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs50th IEEE International Symposium on Circuits and Systems (ISCAS 2017) (2017)
A digital calibration technique for wide-band CT MASH ΣΔ ADCs with relaxed filter requirementsIEEE International Symposium on Circuits and Systems 2016 (ISCAS), 22-25 May 2016, Montreal, Canada (2016)
A wideband RF mixing-DAC achieving IMD<-82 dBc up to 1.9 GHzIEEE Journal of Solid-State Circuits (2016)