Julien Schmaltz is an Associate Professor and Chair of Rigorous Industrial System Design in the Department of Mathematics and Computer Science at Eindhoven University of Technology (TU/e). He is a member of the Model Driven Software Engineering Section. His primary research interests are related to the application of formal methods to hardware and software systems. In particular, his group is working on hardware verification techniques for on-chip networks and the development of formal models for the verification and certification of safety-critical and high-assurance systems. This research is supported by NWO, Intel Corporation, and the European Commission. His group’s main research activities are related to: MaDL (Micro-architectural Description Language) which denotes a formal language to represent and analyze architectural models of hardware and software systems; The MaDL Whiteboard design environment that turns the techniques developed for the textual MaDL language into graphical and practical solutions; GeNoC (Generic Network-on-Chip), which denotes a formal theory of communication network architectures; CISK: a generic model of a Controlled Interruptible Separation Kernel, used within the EURO-MILS project to support the high-level modelling of an industrial Separation Kernel.
Julien Schmaltz received his education at the Université Joseph Fourier (Grenoble I), Polytech Grenoble and the University of Lille. After graduating, he worked as a postdoctoral fellow at Saarland University, Germany, at Radboud University, Nijmegen, the Netherlands and as an Assistant Professor at Open Universiteit Nederland (Dutch Open University). He joined TU/e as an Assistant Professor in 2014 and became an Associate Professor in 2016. Julien has regularly published in leading journals, such as IEEE Transactions on Parallel and Distributed Systems, Journal of Automated Reasoning and ACM Transactions on Design Automation of Electronic Systems. He has been track-chair at the Design Automation and Test Europe conference (three times), chair of the International Workshop on the ACL2 Theorem Prover and Its Applications (twice), and chair of the 2nd International Conference on Interactive Theorem Proving (ITP). He has contributed to the book Formal verification of communications in networks-on-chips. He has also contributed to more than 50 international workshops and conferences.
Formal micro-architectural analysis of on-chip ring networks55th Annual Design Automation Conference, (DAC2018) (2018)
Automatic generation of hardware checkers from formal micro-architectural specifications21st Design, Automation and Test in Europe Conference and Exhibition (DATE 2018) (2018)
Modelling information routing with noninterferenceInternational Workshop on MILS: Architecture and Assurance for Secure Systems (2016)
Process algebra semantics & reachability analysis for micro-architectural models of communication fabricsACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2015) (2015)
Automatic extraction of micro-architectural models of communication fabrics from register transfer level designs2015 Design, Automation & Test in Europe Conference & Exhibition (DATE, Grenoble, France, March 9-13, 2015) (2015)
- Software specification
- Hardware verification
- Kick-off meeting CSE-Softw. Science
- Kick-off meeting Web Science
- Kick-off meeting CSE-System Science
No ancillary activities