Kees Goossens is Full Professor of Real-time Embedded Systems in the Electronic Systems group of the Department of Electrical Engineering at Eindhoven University of Technology (TU/e). He focuses on composable (virtualized), predictable (real-time), low-power embedded systems, supporting multiple models of computation. At Topic Embedded Products, Goossens works on real-time dependable dynamic partial reconfiguration in FPGAs.
Early in his research, he investigated the formal verification of hardware, in particular by using semi-automated proof systems in conjunction with formal semantics of hardware description languages such as ELLA and VHDL. At NXP Semiconductors, Goossens worked on real-time networks on chip for consumer electronics, then on on-chip communication protocols and memory management. He led the team that defined the Aethereal network on chip for consumer electronics.
Goossens has been editorial board member for the ACM Transactions on Design Automation of Electronic Systems (TODAES) since 2009 and associate editor for the Springer Journal of Design Automation of Embedded Systems (DAEM) since 2006, and he has been guest editor for several special issues on networks on chip.
He is author of 24 patents, and he has published four books and over 175 articles, with four paper awards.
Kees Goossens completed his PhD at the University of Edinburgh in 1993. He held several short-term post-doctoral positions at the University of Edinburgh, the Universidade Federal de Pernambuco (Brazil) and Universita di Roma "La Sapienza" (Italy), before becoming a senior principal research scientist at Philips and then NXP Semiconductors in 1995, a position he held for 14 years. In 2007, he was appointed Full Professor at Delft University of Technology (TU/Delft). In 2010, Goossens became Full Professor at Eindhoven University of Technology (TU/e). Since 2016, Goossens has been working as a System Architect for Topic Embedded Products.
NoC-based multiprocessor architecture for mixed-time-criticality applicationsHandbook of hardware/software codesign (2017)
The aethereal network on chip after ten years: Goals, evolution, lessons and futureProc. Design Automation Conference (DAC), 2010 47th ACM/IEEE, Anaheim, CA, 13-18 June 2010 (2010)
Exploiting expendable process-margins in DRAMs for run-time performance optimizations17th Design, Automation and Test in Europe Conference and Exhibition (DATE 2014) (2014)
Communication-centric SoC debug using transactions12th IEEE European Test Symposium, ETS 2007, 20 May 2007 through 24 May 2007, Freiburg (2007)
Power/performance trade-offs in real-time SDRAM command schedulingIEEE Transactions on Computers (2016)
- Systems engineering
- ICT Design and Teamwork - from idea to prototype
- Embedded systems laboratory
- Systems engineering
- Kick-off meeting ES-systems on chip
- System Engineering
- Werkzaamheden als systeem architect, Topic Products