Performance limitations in high-speed continuous-time ΣΔ ADC

Many applications, such as mobile phones, car radios, base-station receivers, etc., demand Analog-to-Digital Converters (ADC) with large signal bandwidth (BW) and high resolutions. However, Nyquist ADCs require large input capacitances determined by thermal noise requirements in order to attain high resolution. These need to be driven by power-hungry linear input buffers, while thermal noise still limits their resolution and clock jitter ruins their sample-and-hold (S/H). On the contrary, continuous-time (CT) ΣΔ ADCs can push clock jitter and thermal noise errors to high frequencies, which consequently can be filtered out through decimation filters.

The application domains of several ADC architectures are shown in Figure 1. Nyquist ADC’s have already achieved very large bandwidths. Extending their performance via approach (1) is difficult as it requires large S/H input capacitors. The alternative approach (2) is to extend the bandwidth of CT ΣΔ ADCs. They have inherent anti-alias filtering and require no S/H, which results in low power consumption. Moreover, many errors are noise shaped by the ΣΔ loop. ΣΔ ADCs can exchange time for amplitude resolution and hence can directly benefit from the continuous scaling of the CMOS IC technologies.

Input signal BW up to 150 MHz with dynamic range (DR) about 70 dB are already demonstrated with ΣΔ ADCs. To go beyond, sampling frequencies in the order of tens of GSample/s will be required. ADC’s stability must be ensured and sufficient quantizer gain must be guaranteed. Multi-bit quantizers and feedback digital-to-analog converters (DAC) help improving the resolution, and make the ADCs less sensitive to clock jitter. However, non-linearity of the feedback DACs degrades the ADC resolution, which needs to be countered with linearization techniques. Thus, deep research is required to point out what are the performance limitations in ultra-high-speed CT ΣΔ ADCs.

This Master project will attempt to answer parts of the research question about these performance limitations and subsequently will demonstrate some solutions that can contribute to going beyond the present state-of-the-art. 

The successful student candidate will have the opportunity to specialize in some of the following fields: system simulation, architecture design, Verilog-a modelling, transistor level circuit design and simulation, layout, and chip measurements, using industry-standard tools such as MATLAB, Cadence Virtuoso. Contacts and consultations with our industrial partners are possible.

Supervisor: Georgi Radulov, Flux 7.089, tel. 5131

Project duration: 9 months