Research on low power amplifiers for multi-GS/s high-resolution pipeline ADCs

In multi-GS/s high-resolution pipeline ADCs, the sample-and-hold amplifier and residue amplifier in the first pipeline stage are required to have high gain-bandwidth product, high linearity and low noise simultaneously, which makes them the most challenging circuit building blocks and consume major part of the power budget in such ADCs. The continuous scaling of CMOS technologies also brings both challenges and opportunities for the amplifier design. On one hand, reduction in voltage supply and gate leakage negatively affect the dynamic range and linearity, while on the other hand, newer process technologies offer transistors with improved bandwidth and matching. In order to exploit the advantages brought by scaled CMOS technologies, innovation in amplifier architectures is required. Besides performance, minimizing power consumption is also very important in most of the applications. Improving the power efficiency of the amplifier by reducing the unnecessary static current or exploiting the digital computational power to eliminate circuit non-idealities have been proved to be effective ways but also requires innovation which makes amplifier design for such ADCs an interesting research topic.

The goal of this research task is to understand speed/noise/linearity tradeoffs of various existing amplifier topologies suitable for GHz rate high-resolution pipeline ADCs, innovate and design low power amplifiers (used as the sample-and-hold amplifier or residue amplifier) suitable for a multi-GS/s pipeline ADC with SNDR >60dB using advanced CMOS technology (e.g. 40nm).

In this project, together with NXP colleagues, the student is expected to carry out the following tasks: 

  • Literature study of amplifier architectures suitable for GHz rate and high resolution pipeline ADCs and summarize their tradeoffs; 
  • Study the pipeline ADC architecture (could also be a hybrid pipelined SAR ADC) and derive specifications for the amplifier for an ADC with multi-GS/s and SNDR>60dB;
  • Innovate, design and implement an amplifier that meets the target specifications; 
  • Document and present the research, design and simulation results. 

Contact person:
Dr. ir. Yu Lin
Principal Scientist
BU Automotive, R&D BL Car Infotainment & Driver Assistance
NXP Semiconductors
High Tech Campus 46 - 1.16, 5656AE Eindhoven, The Netherlands