Optical metrology is a key technology needed for the production of integrated circuits via lithography and its performance is driven by Moore's law of relentless shrink of feature sizes. To enable high-performance optical metrology, well-designed metrology targets are required that can be put on a wafer reliably. Target design and analysis for a proper optical response is typically done via simulations, which need to be increasingly accurate and time-effective, to cope with the ever tightening specifications of the semiconductor roadmaps. The current project aims at the construction of advanced accurate and efficient numerical modeling for optical metrology targets, including the coupling with neighboring product structures on a chip.