Automated SAR ADC Design for IoT

Background

Analog-to-Digital Converter (ADC) is a mixed-signal bridge between the analog world (analog front-end) and the digital world (DSP) as shown in Figure 1. In IoT (Internet-Of-Things) applications, the resolution and the sampling rate of the ADC need to be configurable to cope with different standards for optimal power efficiency. The specification of the ADC can vary significantly, e.g., kSps~MSps for sampling rate and 8b~14b for resolution. So far, most of the ADCs needs to be custom-designed to reach the desired performance, thus increasing the design cost. Alternatively, automation method can be developed, enabling a great reduction of the re-design effort.

ADC design automation effort has also been explored [5-8], however, has not reached a milestone compared to that of PLLs [1-4]. Therefore, it is still a great challenge to increase the automation level while still maintaining performance, especially for the relatively high resolution ADCs. The aim of the project is to further explore the design automation method for ADCs, and increase the level of automation, meanwhile maintaining performance in particular for high resolution ADCs.

Scope

The candidate is required to have a good general knowledge of SAR ADCs, experience in analog and mixed-signal circuit design, and general understanding of algorithms or calibration principles. Being familiar with SKILL and/or Pcell is a plus. Being familiar with simulation and layout in cadence is a plus. The project will focus on SAR ADC design automation, in particular it will be schematic automation and/or layout generation automation and/or additional techniques/circuits to maintain performance. The project will start with a short literature survey and problem analysis, then focus on algorithm design and circuit implementation. 

Tasks

  • Study concept of SAR ADCs and survey on state-of-the-art ADC automation development.
  • Analysis problems and proposal solutions for sub-blocks.
  • Design and implementation of the proposed solution in a test chip.
  • Tape-out of the test chip and measurements for verification.
  • Writing final report and presentation of the results.

Supervisors

Ming Ding from Holst Centre/imec; Pieter Harpe from TU/e

Reference:

[1] W. Deng, “A 0.022 mm 2 970µW dual-loop injection-locked PLL with− 243dB FOM using synthesizable all-digital PVT calibration circuits”, ISSCC 2013.

[2] W. Deng, “A 0.0066 mm 2 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique”, ISSCC 2014

[3] W. Deng, “A 0.048 mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique”, ISSCC 2015

[4] H. C. Ngo, “A 0.42ps-Jitter -241.7dB-FOM Synthesizable Injection-locked PLL with Noise-Isolation LDO”, ISSCC 2016.

[5] S. Weaver, B. Hershberg, and U.-K. Moon, “Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells,” Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 61, no. 1, pp. 84–91, 2014.

[6] A. Waters and U.-K. Moon, “A Fully Automated Verilog-to-layout Synthesized ADC Demonstrating 56dB-SNDR with 2MHz-BW,” in IEEE Solid-State Circuits Conference (A-SSCC), 2015, pp. 1 – 4.

[7] C. Wulff and T. Ytterdal, “A Compiled 3.5fJ/conv.step 9b 20MS/s SAR ADC for Wireless Applications in 28nm FDSOI,” in ESSCIRC, 2016, pp. 177 – 180.

[8] C.-P. Huang, J.-M. Lin, Y.-T. Shyu, and S.-J. Chang, “A Systematic Design Methodology of Asynchronous SAR ADCs,” IEEE Transactions on very large scale integration systems, vol. 24, no. 5, pp. 1835 – 1848, May 2016.