High-level investigation, modelling and implementation of a Sigma-Delta ADC for on-chip radar systems
This project will investigate optimal sigma delta ADC’s for radar applications. Radar poses special requirement on the dynamic range for optimal performance (14-18 bits over a bandwidth of some MHz). However, due to the oversampling nature of the ADC, the resulting data is redundant. In practice the sigma delta ADC is followed by filtering and down-sampling to reduce the bit-rate. In this project the combination of radar signal processing will also be taken into account to come to an optimal overall implementation.
A generic view of a radar system is illustrated in Fig. 1. The radar chip transmits signals. They are reflected by an object and received back in the chip. A Sigma-Delta ADC digitizes the received signals and based on their properties we can determine the location of the object.
This final Master project aims at providing answers on key questions about what the most optimal architecture for such a Sigma-Delta ADC should look like. What architecture? What power consumption? How the specifics of the radar system can be optimally taken into account? ETC.
- Literature survey on Sigma-Delta ADC architecture;
- Explore system requirements of the radar application;
- System-level model of selected Sigma-Delta ADC architectures in:
- Transistor-level model of chosen optimal Sigma-Delta ADC architecture in:
- Thesis writing and documentation in Omniradar, Eindhoven;
Level of topic: MSc
Master's programs: Electrical Engineering
Duration: 9-12 months