High-speed offset compensated comparator in 28nm

A high-speed voltage comparator circuit is required for a demanding potentially noisy embedded application in 28nm CMOS. The required speed of operation is greater than 2GHz with an input referred sigma offset of less than 3mV after considering post-layout extraction and process spreads. Offset cancellation should be used, preferably using dynamic offset cancellation. The common mode range is 0.6V to 1V for a 1.2V supply. The CMRR and PSRR need to be high. Both thin-ox and thick-ox transistors are available as well as access to a 1.8V supply if needed. The overall design should be optimised for speed, accuracy, power consumption and good noise rejection. 

The project will be conducted initially at the MSM group in TU/e after which it will move to the Endura Technologies design centre in Dublin Ireland.

Supervisor:                              Georgi Radulov
Contact person in industry:    dr.ir. Patrick Quinn, Endura Technologies, Dublin
Project duration:                      9 months