Data Converters research projects

Current projects

Power-efficient reference-including ADCs
Sponsor
DurationStart 10-2013, End 10-2017
PhD studentMaoqiang Liu
SupervisorPieter Harpe
Description

This project studies the combination of reference generation and ADCs, and aims to optimize the power consumption and chip-area for the total system.


This project so far resulted in 1 ISSCC, 2 ESSCIRC, 1 JSSC and 1 ISCAS paper. The ISSCC/JSSC paper discusses the implemented design of low-power reference generator combined with an ADC. Duty cycling techniques are used to minimize the overall system power. The obtained results prove that the references can be generated at an acceptable cost in terms of power overhead. The ESSCIRC papers discuss further techniques to reduce ADC power consumption and to integrate an efficient reference driver with ADC correction techniques. The ISCAS paper is a further development of generating reference voltages dynamically, to allow easy burst-mode operation which is applicable to (for instance) IoT systems.

PERFECT SDM: Power Efficient Radio-Frequency Extension of Continuous-Time Sigma-Delta Modulators
SponsorSTW project
DurationStart 2012, End 2020
PhD studentsChenming Zhang, Qilong Liu
SupervisorGeorgi Radulov
DescriptionPERFECT SDM project explores the bandwidth, resolution and sampling frequency limits of continuous-time RF bandpass sigma-delta modulators and consequently aims to expand these limits in order to enable future low-cost high-performance integrated receivers for e.g. phased-array base-station and multi-standard radio applications. This project will develop technologies that will enable new power-efficient, flexible and versatile RF-bandpass ADCs while also being economically highly relevant to many existing and future applications like cellular phones, car radios, integrated (phased-array) base-station receivers and cognitive radios.

Completed projects

Multifunctional Analog-to-Digital Converters for
Emerging Mobile and Medical Applications
SponsorNWO VENI
DurationStart 01-10-2013, End 31-09-2016
ResearcherPieter Harpe
Description

The key-objective of this project is to develop concepts and to realize chip-implementations for truly multifunctional ADCs. Moreover, these ADCs should also achieve a power-efficiency beyond current state-of-the-art point-optimized solutions. The flexibility target will be chosen such that the design covers a very broad range of mobile and medical applications.

 

This project resulted in two ISSCC publications and one JSSC publication. The first work achieved a breakthrough in SAR ADC precision with best-in-class power efficiency. The second work implemented a full ECG acquisition frontend while consuming only 3nW of power, by far the lowest power for any acquisition platform. This latter work received the ISSCC 2015 Distinguished Technical Paper Award. A broader article was also written in Bits and Chips, “Topchips uit de lage landen”, February 2015. Furthermore, one of the designed multifunctional data converters was transferred to the business for utilization in an emerging medical application. The achievements within the scope of this project also resulted in invited presentations at the NanoNetwork workshop in 2014, Kempenhaeghe Symposium in 2015, a VLSI Symposium short course in 2015, a tutorial at ISSCC 2016, a day-long lecture at Topics-on-Microelectronics 2016, invited company presentations at various major companies, and lectures at National Taiwan University, Hong Kong University of Science and Technology and University of Macau.

SLIM (Smart LImit-cycle Modulators)
SponsorSTW project
DurationStart 12-09-2011, End 12-09-2015
PhD studentsKetan J. Pol and Jingjing Hu
SupervisorHans Hegt
DescriptionThe project concerns adaptive and configurable Sigma Delta ADCs. The goal is to use the non-linear theory of SDMs previously established in our group and extending to design high accuracy, low power Sigma Delta ADCs. Such ADCs are capable of adapting to changing operation conditions and configurable according to changing user requirements.
Highly linear high-frequency Mixing-DACs
SponsorIDT - Integrated Device Technology
DurationStart 01-04-2010, End 15-05-2014
PhD studentElbert Bechthum
SupervisorGeorgi Radulov
DescriptionIn an RF transmitter, the function of the mixer and the DAC can be combined in a single block: the Mixing-DAC. For the generation of multicarrier GSM signals in a basestation, high dynamic linearity is required, e.g. SFDR>85dBc, at high output signal frequency, e.g. fout = 4GHz. This represents a great challenge which cannot be addressed efficiently by current available hardware or state-of-the-art published solutions.

This project aims at realizing both the D/A and Mixing functions at very high frequencies in a very linear manner.
Power-efficient high-resolution low-bandwidth switched-capacitor sigma delta modulators
Sponsor
DurationStart 15-03-2009, End 14-03-2013
PostdocSerena Porrazzo
SupervisorEugenio Cantatore
DescriptionThe research focuses on power-efficient high-resolution low-bandwidth switched-capacitor (SC) sigma delta modulators (SDMs).
This study is applied to the digitization of biomedical signals and aims at implementing a reconfigurable SDM, with power efficiency as much as possible constant and optimal, despite the change in desired resolution and bandwidth.