Supervisory control synthesis and realization for a lock family

In the coming decades, numerous navigation locks have to be renovated or replaced in the Netherlands. This project focuses on synthesising supervisory controllers and implementing them on the control hardware.

PhD Candidateir. Ferdie Reijnen
Supervisor: dr.ir. Asia v.d. Mortel-Fronczak, dr.ir. Michel Reniers
Promotor: prof.dr.ir. Wan Fokkink
Project Financing: Rijkswaterstaat
Project Period: November 2016 - October 2020

The complexity of the design, realization and maintenance of operation and control systems for civil infrastructures is increasing rapidly. Infrastructures are transformed from just civil systems to cyber-physical systems. Systems engineering (SE) methodologies are used in the industry to cope with this complexity. Several SE methods are used within Rijkswaterstaat (RWS). Recently, within the high tech systems industry models are introduced in the SE methods. This has resulted in model-based systems engineering (MBSE) methods. The aim of MBSE is to develop and use models of the architecture and dynamics of a system to increase the understanding and the quality of the design of the system.

Supervisory control synthesis (SCS) is a formal method that derives a supervisor from a model of the uncontrolled system and a model of the control requirements. This research focusus on integrating fault-tolerant control in the SCS framework. Furthermore, methods to automatically derive correct control code from the supervisor model are considered.