Power-efficient layered turbo decoder processor
ConferentiebijdrageDielissen, J.T.M.H., Meerbergen, van, J., Bekooij, M.J.G., Harmsze, F., Sawitzki, S., Huisken, J. & van der Werf, A. (2001). Power-efficient layered turbo decoder processor. Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001, Munich, 13-16 March 2001 (pp. 246-251). Piscataway: Institute of Electrical and Electronics Engineers (IEEE). In Scopus Cited 3 times.
Turbo decoding offers outstanding error correcting capabilities, that will be used in wireless applications like the Universal Mobile Telecom Standard (UMTS). However the algorithm is very computational intensive, and therefore an implementation on a general purpose programmable DSP results in a power consumption which reduces the applicability of turbo decoding in hand-held applications. In this paper we present a solution based on a layered processing architecture. This architecture includes an application specific Very Long Instruction Word (VLIW) processor, a data flow processor, and hard-wired execution units in a hierarchical way. The power consumption of this solution is an order of magnitude better than the implementation on a current state of the art, power efficient general purpose DSP.