An FPGA design flow for reconfigurable network-based multi-processor systems on chip
ConferentiebijdrageKumar, A., Hansson, M.A, Huisken, J. & Corporaal, H. (2007). An FPGA design flow for reconfigurable network-based multi-processor systems on chip. Design, Automation & Test in Europe Conference & Exhibition, 2007 : DATE '07 ; 16 - 20 April 2007, [Nice, France] (pp. 1-6). Piscataway: Institute of Electrical and Electronics Engineers (IEEE). In Scopus Cited 48 times.
Multi-processor systems on chip (MPSoC) platforms are becoming increasingly more heterogeneous and are shifting towards a more communication-centric methodology. Networks on chip (NoC) have emerged as the design paradigm for scalable on-chip communication architectures. As the system complexity grows, the problem emerges as how to design and instantiate such a NoC-based MPSoC platform in a systematic and automated way. This paper presents an integrated flow to automatically generate a highly configurable NoC-based MPSoC for FPGA instantiation. The system specification is done on a high level of abstraction, relieving the designer of error-prone and time consuming work. The flow uses the state-of-the-art /Ethereal NoC, and silicon hive processing cores, both configurable at design- and run-time. The authors use this flow to generate a range of sample designs whose functionality has been verified on a Celoxica RC300E development board. The board, equipped with a Xilinx Virtex II 6000, also offers a huge number of peripherals, and shows how the insertion is automated in the design for easy debugging and prototyping