Comparison of an æthereal network on chip and a traditional interconnect for a multi-processor DVB-T system on chip

Conferentiebijdrage

Bartels, C.L.L., Huisken, J., Goossens, K.G.W., Groeneveld, P.R. & Meerbergen, van, J. (2006). Comparison of an æthereal network on chip and a traditional interconnect for a multi-processor DVB-T system on chip. 2006 IFIP International Conference on Very Large Scale Integration : Nice, France, 16 - 18 October 2006 (pp. 80-85). New York: Institute of Electrical and Electronics Engineers (IEEE). In Scopus Cited 6 times.

Lees meer: DOI      Medialink/Full text

Abstract

 

Growing complexity of multiprocessor systems on chip (MP-SoC) requires future communication resources that can only be met by highly scalable architectures. Networks-on-Chip (NoCs) offer this scalability and other advantages like modularity, quality-of-service (QoS), possibly smaller area footprint and lower power dissipation. Although many papers describe the advantages of NoCs and describe techniques to apply NoCs on certain application domains, few have actually employed the complete design chain to make a netlist level implementation and area comparison [1], [2]. This paper describes the application of the æthereal NoC to an existing bus-based MP-SoC design and an area comparison with the original interconnect structure down to netlist level.