A 13bits 4.096GHz 45nm CMOS digital decimation filter chain with Carry-Save format numbers
TijdschriftartikelHuang, Yanxiang, Kapoor, A., Rutten, R. & Pineda de Gyvez, J. (2015). A 13bits 4.096GHz 45nm CMOS digital decimation filter chain with Carry-Save format numbers. Microprocessors and Microsystems, 39(8), 869–878-869–878. In Scopus Cited 3 times.
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In this paper we analyze the architecture of a 13 bits 4.096. GHz multi-stage decimation filter for multi-standard radio receivers. It also explores the benefits of Carry-Save format numbers in this decimation filter. After trading off between area and power consumption, we propose to use shift-and-adder for high data rate decimation stages and hardware multiply-accumulator for low data rate stages. The proposed decimation filter chain exploits the advantage of all architectures and exhibit the best area-power trade-off. It is implemented using 45 nm CMOS technology. The proposed design reduces power by 13.7% without area overhead, compared with a conventional filter chain using only binary number.