Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications

Conferentiebijdrage

Artes, A., Ayala, J.L., Sathanur, A.V., Huisken, J. & Catthoor, F. (2011). Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications. 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC) (pp. 136-141). In Scopus Cited 3 times.

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Abstract

 

Instruction memory organization is pointed out as one of the major sources of energy consumption in embedded systems. As embedded systems are characterized by restrictive resources and low energy budget, any enhancement in this component allows not only to decrease the total energy consumption, but also to have a better distribution of the energy budget throughout the system. This paper presents a self-tuning banked loop buffer architecture, which is based on a run-time loop buffer controller that optimizes both the dynamic and leakage energy consumption of the instruction memory organization. Results show that using banking in loop buffer architectures leads to higher reduction in the total energy consumption of the instruction memory organization if the tuning approach is applied sparingly. Based on post-layout simulations, our approach improves the total energy consumption by average of 20% in comparison with a loop buffer architecture based on a single monolithic memory, and more than 90% in comparison with instruction memory organizations without loop buffer architectures.