Standard cell sizing for subthreshold operation


Liu, B., Ashouei, M., Huisken, J.A. & Pineda de Gyvez, J. (2012). Standard cell sizing for subthreshold operation. Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE, 3-7 June 2012, San Francisco, USA (pp. 962-967). New York: Association for Computing Machinery, Inc. In Scopus Cited 21 times.



Process variability severely impacts the performance of circuits operating in the subthreshold domain. Among other reasons, this mainly stems from the fact that subthreshold current follows a widely spread Log-Normal distribution. In this paper we introduce a new transistor sizing methodology for standard cells. Our premise relies on balancing the N and P network currents based on statistical formulations. Our approach renders more robust cells. We observe up to 57% better performance and 69% lower energy consumption on a set of ISCAS circuits when they are synthesized with our library as opposed to a commercial library in a CMOS 90nm technology.