AVISPA: a massively parallel reconfigurable accelerator

Conferentiebijdrage

Leijten, J., Burns, G., Huisken, J., Waterlander, E. & van Wel, A. (2003). AVISPA: a massively parallel reconfigurable accelerator. Proceedings. International Symposium on System-on-Chip. (pp. 165-168). In Scopus Cited 9 times.

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Abstract

 

Standards and market uncertainties, non-recurring engineering costs, and lack of access to (or knowledge of) application IP requires the next generation of embedded computing platforms to be fully programmable. In terms of silicon cost and power, practical yet fully programmable embedded computing platforms are enabled by reconfigurable accelerators that replace fixed ASIC coprocessors in current standard platforms. The AVISPA reconfigurable accelerator is a landmark commercial offering, embodying the processor and compiler design technology that bridges the industry to fully programmable platforms in applications with extreme real-time performance requirements. The accelerator and its associated programming tools were created using a propriety automatic processor and tool generation flow. As a result AVISPA could be easily tailored to achieve high computational efficiency (MOPS/W) in the acceleration of critical digital signal processing kernels for software-defined radio. An innovative C-compiler, generated from the same methodology, aggressively exploits massive instruction parallelism in application kernels mapped onto the core. This paper explains the concepts behind AVISPA, discusses its architecture, gives details on its supporting compiler, and provides benchmarks for a number of application kernels.