Hierarchical buffered segmented bit-lines based SRAM


Sharma, V., Cosemans, S., Dehaene, W., Catthoor, F., Ashouei, M. & Huisken, J. (2011). Hierarchical buffered segmented bit-lines based SRAM. Patent No. US2011305099.



A semiconductor memory device is disclosed. In one aspect, the device includes memory blocks with memory cells connected to a local bit-line, each local bit-line being connectable to a global bit-line for memory readout. There are also pre-charging circuitry for pre-charging the bit-lines and a read buffer for discharging the global bit-line during a read operation. The local bit-lines are pre-charged to a predetermined first voltage substantially lower than the supply voltage (VDD) of the memory device. A segment buffer is provided between each local bit-line and an input node of the respective read buffer. The segment buffer activates the read buffer during the read operation upon occurrence of a discharge on the connected local bit-line.