Optimizing the power and area performance of analog circuit design

For his PhD research Hanyue Li aimed to optimize the power and area performance of analog circuitry from a system perspective. There are two main conclusions of his work. The proposed duty-cycling techniques are applied to different blocks in a analog signal processing chain. This is beneficial in terms of power consumption from a system perspective. Furthermore the compact layout technique is adopted in low-resolution SAR ADCs. This can significantly reduce the chip area, thus reducing the area cost when multi-channel ADCs are required in applications such as biomedical signals acquisition.

Li investigated duty cycling techniques in various analog blocks for the purpose of saving power, and developed compact layout techniques to reduce the area of low-resolution SAR ADCs. Both theoretical analysis and silicon implementations are provided to validate the effectiveness of the proposed methods.

Excellent power and area efficiency

A discrete-time noise-shaping SAR ADC is explored first with an energy-efficient duty-cycled residue amplifier and a mismatch error shaping technique. After that, the noise-shaping SAR ADC architecture is extended to continuous-time operation by using a duty-cycled loop filter, so that it can have an inherent anti-aliasing function. To reduce the power consumption of the ADC input driver and anti-aliasing filter, duty-cycling approaches are applied to these two blocks without causing significant performance degradation. Finally, different area reduction strategies are developed for SAR ADCs with a resolution from 8 to 11 bits to achieve the lowest area cost. These designs have shown their potential to be used in various energy-constrained applications thanks to their excellent power and area efficiency.

Title of PhD thesis: Duty Cycling and Compact Layout Techniques in ADCs and Analog Front-ends. Supervisors: Dr. Pieter Harpe and Prof. Eugenio Cantatore.