Optimization of Cell-Aware Test
Zhan Gao defended her PhD thesis at the department of Electrical Engineering on March 10th.
Defects can occur in microchip manufacturing, and this can lead to malfunctions. To guarantee the quality of chips, every chip is subject to testing. Test quality, test cost, and test development time are the three key performance indicators of a chip test. Cell-aware test is a new test approach for logic circuits in a chip, which is becoming more popular in the semiconductor industry due to its effectiveness and efficiency in identifying manufacturing defects. In her PhD research, Zhan Gao presents an update of the cell-aware test methodology and tool flow to optimize its three test performance indicators. The developed algorithms are being now used by some top semiconductor companies.
The logic part in an integrated circuit (IC) is typically tested by various automatic test pattern generation (ATPG) approaches. Cell-aware test (CAT) is a new ATPG-based approach for logic circuits. It explicitly targets defects inside library cells and significantly increases test quality compared to conventional ATPG-based approaches that cover cell-internal defects only serendipitously.
Even though CAT's methodology has been defined and developed for more than ten years, several issues should be revolved to optimize CAT results. The IC test has three key performance indicators (KPIs): test quality, test cost, and test development time, in order of decreasing importance. In her PhD thesis, Zhan Gao outlines the approaches that she investigated to optimize the three test KPIs for CAT.
What is CAT?
CAT consists of two phases; namely library characterization and cell-aware ATPG.
In library characterization, dedicated analog simulation is performed to determine which cell-level test pattern detects certain cell-internal defects. This information is encoded in a defect detection matrix (DDM) per library cell.
In cell-aware ATPG, chip-level test patterns are generated per circuit design by expanding the cell-level test patterns to chip level, according to the defect-pattern detection information in DDMs. DDMs, as the interface between both CAT Phases, affect the CAT KPIs. Gao and her collaborators (including Kees Goossens and Said Hamdioui) used three elements of DDMs: cell-internal defects, cell-level test patterns, and the detection result per defect-pattern tuple to set specific goals and propose corresponding solutions, with the aim of optimizing the CAT KPIs.
The particular set of cell-internal defects under consideration affects both test quality and test development time. Too few defects mean the test might be missing defects; this can negatively impact the test quality. Too many defects imply unnecessary time-consuming analog simulations during the library characterization, which increases test development time.
Therefore, Gao proposes an optimized library characterization flow that not only identifies all possible cell-internal defects to guarantee the test quality, but also reduces the library characterization time. The experimental results on an GPDK045 45nm library show that for 476 library cells the new library characterization flow saves 97.3% defect simulation time compared to simulating all potential defects.
Cell-level test patterns
Cell-level test patterns, as the starting points of the cell-aware ATPG, influence the cell-aware ATPG results with respect to fault coverage, test pattern count, and compute time. Fault coverage is an indicator of test quality; test pattern count affects test cost; and ATPG compute time is a part of test development time.
Gao proposes two algorithms to manipulate cell-level test patterns in DDMs and optimize cell-aware ATPG results. Experimental results using the two algorithms in conjunction on twelve circuits show average reductions of 43% of non-covered faults and 10% in chip-pattern count compared to the ATPG results, which are based on the original DDMs.
The defect simulation fact is that in a majority of defect-pattern tuples, the defect cannot be detected by the pattern. Based on our theoretical analysis, many undetectable tuples can be identified only on the basis of the topology of the cell’s transistors netlist. This is known as as logical undetectability.
In her thesis, Gao outlines an efficient algorithm that performs a structural analysis of library cells to identify all logically undetectable tuples, which then can be excluded from the time-consuming analog simulation. With this, structural analysis is a lot faster than the analog simulation and the combination delivers significant speed-ups. For 476 standard cells from Cadence’s GPDK045 library, we achieve a 47% reduction in overall characterization time.
All optimization methods and experiments in Gao’s research were implemented using the state-of-the-art CAT tool flow that was developed by Cadence Design Systems with the collaboration of Gao and her collaborators. The original results of this CAT tool flow are used as the baseline for comparisons with her experimental results. Three of Gao’s algorithms were already a part of the Cadence commercial tool and are being used by some top ten semiconductor companies.
Title of PhD thesis: Optimization of Cell-Aware Test. Supervisors: Kees Goossens and Said Hamdioui (external).
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