The Photonic Integration group (PhI, department of Electrical Engineering) uses the NanoLab facilities
- For fabrication of InP-based Photonic Integrated Circuits (PICs)
- For development of advanced InP and Silicon based photonic integration technology.
The group uses a major part of the equipment available in the Nanolab:
InP-based layer stacks for Photonic ICs are grown in the two Nanolab MOVPE kits (single wafer and multiple wafer reactor).
For patterns with very critical dimensional accuracy requirements, such as waveguide patterns and grating structures, we use a 193 nm scanner (ASML 5500/1100) with an ultimate resolution of 100 nm. It is a unique tool which has been adapted for use with 3” and 4” InP or GaAs wafers in close cooperation with ASML. For patterns with very small features we use a Raith e-Line Electron-Beam machine. For the less critical lithography steps we have two I-line systems: an automatic ASML wafer stepper and a manual Karl-Suss Mask aligner.
For deposition of SiO and SiN hard mask and passivation layers we use PE-CVD equipment and E-beam evaporation equipment (?). For deposition of metals we use dedicated E-beam evaporation and sputtering equipment. Metal deposition is usually done using lift-off technology.
We use dedicated RIE and ICP-RIE equipment for etching InGaAsP/InP and dielectric layers (SiO and SiN), and for etching or removing polymer layers (oxygen etch). Further we use the wet benches for a variety of wet etch and cleaning steps.
Rapid Thermal Annealing
Rapid Thermal Annealing is an essential step for forming low-resistance metal contacts.
Bonding and Plating equipment.
Electrical connections to our chips are made using wire bonding or ribbon bonding equipment. Galvanic Electro-plating is used for increasing the thickness, and thus reducing the resistance, of contact lauyers.
A Scanning Electron Microscope (SEM) and a variety of optical microscopes are frequently used for inspection of wafers during or after the processing.