Former Doctoral Candidate
Debashis Dhar
Department / Institute
Group
I am designing a Phase-Locked Loop (PLL) based frequency synthesizer for 60 GHz FMCW radar. The single-chip radars will be used to form a phased-array radar for imaging. My research focus is to synchronize the phases of the PLL output signals from different chips.
Recent Publications
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D. Dhar,P.T.M. van Zeijl,D. Milosevic,H. Gao,P.G.M. Baltus
Analysis of the effect of PFD sampling on charge-pump PLL stability
(2018) -
D. Dhar,P.T.M. van Zeijl,D. Milosevic,H. Gao,P.G.M. Baltus
Noise analysis of a BJT-based charge pump for low-noise PLL applications
(2017) -
D. Dhar,P.T.M. Zeijl,D. Milosevic,H. Gao
Modeling and analysis of the effects of PLL phase noise on FMCW radar performance
(2017)
Ancillary Activities
No ancillary activities